The present invention relates generally to fabrication of interconnect structures within integrated circuits, and more particularly, to using an alloy with at least two dopant elements for an interconnect structure for forming the self-aligned diffusion barrier material for minimized resistance of the interconnect structure.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Thus far, aluminum has been prevalently used for metallization within integrated circuits. However, as the width of metal lines are scaled down to smaller submicron and even nanometer dimensions, aluminum metallization shows electromigration failure. Electromigration failure, which may lead to open and extruded metal lines, is now a commonly recognized problem. Moreover, as dimensions of metal lines further decrease, metal line resistance increases substantially, and this increase in line resistance may adversely affect circuit performance.
Given the concerns of electromigration and line resistance with smaller metal lines and vias, copper is considered a more viable metal for smaller metallization dimensions. Copper has lower bulk resistivity and potentially higher electromigration tolerance than aluminum. Both the lower bulk resistivity and the higher electromigration tolerance improve circuit performance.
Referring to FIG. 1, a cross sectional view is shown of a copper interconnect 102 within a trench 104 formed in an insulating layer 106. The copper interconnect 102 within the insulating layer 106 is formed on a dense dielectric material 109 deposited on a semiconductor wafer 108 such as a silicon substrate as part of an integrated circuit. The dense dielectric material 109 may be a hardmask layer, an etch stop layer, or a capping layer comprised of SiO2 (silicon dioxide) or SiN (silicon nitride) for example. Because copper is not a volatile metal, copper cannot be easily etched away in a deposition and etching process as typically used for aluminum metallization. Thus, the copper interconnect 102 is typically formed by etching the trench 104 as an opening within the insulating layer 106, and the trench 104 is then filled with copper typically by an electroplating process, as known to one of ordinary skill in the art of integrated circuit fabrication.
Unfortunately, copper is a mid-bandgap impurity in silicon and silicon dioxide. Thus, copper may diffuse easily into these common integrated circuit materials. Referring to FIG. 1, the insulating layer 106 may be comprised of silicon dioxide or a low dielectric constant insulating material such as organic doped silica, as known to one of ordinary skill in the art of integrated circuit fabrication. The low dielectric constant insulating material has a dielectric constant that is lower than that of pure silicon dioxide (SiO2) for lower capacitance of the interconnect, as known to one of ordinary skill in the art of integrated circuit fabrication.
Copper may easily diffuse into such an insulating layer 106, and this diffusion of copper may degrade the performance of the integrated circuit. Thus, a diffusion barrier material 110 is deposited to surround the copper interconnect 102 within the insulating layer 106 on the sidewalls and the bottom wall of the copper interconnect 102, as known to one of ordinary skill in the art of integrated circuit fabrication. The diffusion barrier material 110 is disposed between the copper interconnect 102 and the insulating layer 106 for preventing diffusion of copper from the copper interconnect 102 to the insulating layer 106 to preserve the integrity of the insulating layer 106.
Further referring to FIG. 1, an encapsulating layer 112 is deposited as a passivation layer to encapsulate the copper interconnect 102, as known to one of ordinary skill in the art of integrated circuit fabrication. The encapsulating layer 112 is typically comprised of a dielectric such as silicon nitride, and copper from the copper interconnect 102 does not easily diffuse into such a dielectric of the encapsulating layer 112.
As the line width of the interconnect structure is continually decreased, the thickness of the diffusion barrier material 110 is desired to be minimized to in turn minimize the volume of the diffusion barrier material 10 within the interconnect opening. Minimizing the volume of the diffusion barrier material 10 in turn maximizes the volume of the copper conductive fill material 102. Generally, diffusion barrier materials have higher resistance than the copper conductive fill material, as known to one of ordinary skill in the art of integrated circuit fabrication. Thus, maximizing the volume of the copper conductive fill material 102 and minimizing the volume of the diffusion barrier material 110 advantageously results in minimizing the resistance of the interconnect structure.
In the prior art, referring to FIG. 2, a conductive fill material 150 such as copper that is doped with a dopant element such as magnesium is formed to fill the interconnect opening 104. Then, a thermal anneal is performed to form a self-aligned diffusion barrier material 152 of FIG. 3. During the thermal anneal process, the magnesium as the dopant element of the copper conductive fill material 150 diffuses out of the copper conductive fill material 150 toward the walls of the interconnect opening 104 to form the self-aligned diffusion barrier material 152 from a reaction of the magnesium with the dielectric material of the insulating layer 106.
For the insulating layer 106 that is comprised of silicon dioxide (SiO2), the magnesium that reaches the walls of the interconnect opening 104 reacts with the oxygen of the silicon dioxide to form the self-aligned diffusion barrier material 152 that is comprised of magnesium oxide (MgO). The thickness of the self-aligned diffusion barrier material 152 that is formed in this manner may be advantageously smaller than a layer of diffusion barrier material that is deposited in a deposition process, as known to one of ordinary skill in the art of integrated circuit fabrication.
However, in the prior art, when oxygen atoms of the silicon dioxide (SiO2) of the insulating layer 106 are consumed to form the self-aligned diffusion barrier material 152, silicon atoms of the silicon dioxide (SiO2) of the insulating layer 106 are free to diffuse into the conductive fill material 150. When such free silicon atoms diffuse from the silicon dioxide (Si02) of the insulating layer 106 into the conductive fill material 150, the resistance of the conductive fill material 150 increases to disadvantageously form an interconnect structure with higher resistance.
Nevertheless, formation of the self-aligned diffusion barrier material is advantageous for achieving a thinner diffusion barrier material as the dimensions of the interconnect structure are continually scaled down. Thus, a mechanism is desired for forming the self-aligned diffusion barrier material with prevention of the increase of resistance of the conductive fill material.
Accordingly, in a general aspect of the present invention, a conductive fill material with at least two dopant elements is used. A first dopant element is amenable for forming the self-aligned diffusion barrier material with a first dielectric reactant element of the surrounding insulating layer. In addition, a second dopant element is amenable for forming a boundary material with a remaining second dielectric reactant element of the surrounding insulating layer to prevent diffusion of the second dielectric reactant element into the conductive fill material.
In a general aspect of the present invention, for fabricating an interconnect structure formed within an interconnect opening surrounded by dielectric material, the interconnect opening is filled with a conductive fill material comprised of a bulk conductive fill material doped with a first dopant element and a second dopant element that is different from the first dopant element. The dielectric material is comprised of a first dielectric reactant element and a second dielectric reactant element.
A diffusion barrier material is formed from a reaction of the first dopant element of the conductive fill material and the first dielectric reactant element. The first dopant element of the conductive fill material diffuses out of the conductive fill material to the surrounding dielectric material at walls of the interconnect opening during a thermal anneal process. In addition, a boundary material is formed from a reaction of the second dopant element of the conductive fill material and the second dielectric reactant element. The second dopant element of the conductive fill material diffuses out of the conductive fill material to the surrounding dielectric material at the walls of the interconnect opening during the thermal anneal process.
The diffusion barrier material and the boundary material form a self-aligned skin layer on the walls of the interconnect opening between the conductive fill material and the dielectric material. The self-aligned skin layer prevents diffusion of the conductive fill material into the dielectric material, and the formation of the boundary material prevents diffusion of the second dielectric reactant element into the conductive fill material.
In one embodiment of the present invention, the bulk conductive fill material is copper, and the surrounding insulating dielectric material is comprised silicon dioxide. When the first dopant element includes at least one of Mg (magnesium), Ca (calcium), Cr (chromium), and Zr (zirconium) and when the first dielectric reactant element is oxygen of silicon dioxide for the dielectric material, then the diffusion barrier material is comprised of a metal oxide. When the second dopant element includes at least one of Ti (titanium), Co (cobalt), Ni (nickel), and Ta (tantalum) and when the second dielectric reactant element is silicon of the silicon dioxide for the dielectric material, then the boundary material is comprised of a metal silicide.
In this manner, the self-aligned skin layer is comprised of the diffusion barrier material and the boundary material formed at the walls of the interconnect opening. Because the skin layer is formed as self-aligned, the thickness of the diffusion barrier material is smaller than those formed with deposition processes. Such a thin diffusion barrier material maximizes the volume of the conductive fill material within the interconnect opening to minimize the resistance of the interconnect structure formed within the interconnect opening. In addition, formation of the boundary material of the skin layer consumes the remaining second dielectric reactant material to prevent diffusion of the second dielectric reactant material into the conductive fill material such that the resistance of the conductive fill material is not increased.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.